Computer arrangements, including microprocessors and digital signal processors, have been designed for a wide range of applications and have been used in virtually every industry. For a variety of reasons, many of these applications have been directed to processing video data and have demanded minimal levels of power consumption and compactness. Some applications have further demanded a high-speed computing engine that can perform effectively on a real-time or near real-time basis. Many of these video-processing applications have required a data-signal processing circuit that is capable of performing multiple functions at ever-increasing speeds.
Increasing the power and versatility of such computing engines, however, can undermine other important goals. For example, faster computing engines consume more power and circuit real estate, whereas the ideal engine minimizes both power consumption and the amount of circuitry required to implement the computing engine.
Moreover, providing versatility and high power typically exacerbates the circuit real estate problem by requiring various types of processing circuitry, each specialized and selectively activated for different processing functions. This phenomena can be appreciated when comparing, for instance, relatively-slow general-purpose processing in video applications versus specialized video-signal filter processing used for compressing and decompressing video data in real time. Because the specialized processing circuitry is typically optimized to keep up with the real-time speeds of the video data, it is often difficult to provide a single video-data processing circuit that is adequately versatile without providing seemingly excess circuitry useful only for limited applications.
As a more particular example, many video-signal processing applications employ various specialized video-signal processing architectures for high-speed processing functions applied to the video data. These high-speed processing functions include, among many others, general low-pass and high-pass filtering, motion-compensated scan-rate conversion, and scaling and peak filtering. In video-processing applications, these functions are often performed by manipulating data stored to represent the horizontal and vertical lines used to refresh the display data representing the displayed pixels.
In each of the above video-processing applications, there is a significant cost in connection with designing, manufacturing and maintaining the integrated circuits used to provide such functionality. For example, one high-speed implementation operating in a relatively noiseless environment might permit sampling pixel data corresponding to a video frame, e.g., as stored in memory or captured via a camera, at a relatively infrequent rate, and another high-speed implementation might require sampling the pixel data at a relatively frequent rate. The high-speed architectures used to post-process (e.g., filtering) such differently sampled data would typically be implemented differently. In each such application, the costs associated with such architecturally-incompatible architectures are significant.
Accordingly, there is a well-recognized need to develop a relatively compact video-processing architecture that accommodates these multiple functions without a significant loss in data-processing throughput. It has been particularly difficult maintaining the high-throughput and providing an architecture that is sufficiently flexible for use in a wide variety of application; efforts to realize such goals have thus far been competing tensions. The present invention is directed to a data-processing architecture that can deliver a fixed number of pixels to such a video processing stage using a sampling pattern that can be defined from a range of selectable sampling windows.